Various technologies have been disclosed which control the order of priority in packet transfer in communication networks.
Japanese Patent Application Laid-open Publication No. 2012-182807 (hereinafter referred to as “PTL1”) discloses the following technology regarding scheduling of priorities in communication networks. First, packets with high priority levels (hereinafter, referred to as high priority packets) are placed at points progressively closer to the head of a queue instead of being placed at the end of the queue. Second, the points progressively closer to the head of the queue are determined on the basis of a predetermined percentage of a delay requirement of the high priority packet or a predetermined percentage of an expected queuing delay for the high priority packets.
Japanese Patent Application Laid-open Publication No. 2012-239138 (hereinafter referred to as “PTL2”) discloses a priority setting device. The priority setting device acquires a plurality of packets. The transmission nodes and reception nodes of the packets are identical. The priority setting device then sets the priorities of the packets in accordance with inter-packet delays between the packets. For example, the priority setting device calculates first delay amounts, which are statistics of inter-packet delays between the packets, on the basis of acquisition times of the plurality of packets acquired in a predetermined period. The priority setting device then sets the priorities of the packets on the basis of differences between the first delay amounts and a predetermined reference delay amount. The priority setting device also calculates a second delay amount, which is a statistic of the first delay amounts, and employs the second delay amount as the above-described reference delay amount.
On the other hand, in recent LSI (Large Scale Integration) design, a network-on-chip technology in which modules in an LSI chip are interconnected by routers and channels has come to be employed.
For example, Japanese Patent Application Laid-open Publication No. 2009-110512 (hereinafter referred to as “PTL3”) discloses an example of a network-on-chip. The network-on-chip disclosed in PTL3 includes integrated processor blocks, routers, memory communication controllers and network interface controllers. In the network-on-chip, first, each integrated processor block is coupled with a router through a memory communication controller and a network interface controller. Second, each memory communication controller controls communication between an integrated processor block and memory. Third, each network interface controller controls inter-integrated processor block communication through routers.
When a plurality of communications (transfers of packets) from a plurality of ports to a specific port compete with one another, a router in such a network-on-chip employs, for example, a round-robin scheduling method to arbitrate the plurality of communications.